DESIGN AND ANALYSIS OF A DYNAMICALLY RECONFIGURABLE NETWORK PROCESSOR By IAN A. TROXEL A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF ENGINEERING

of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Master of Engineering DESIGN AND ANALYSIS OF A DYNAMICALLY RECONFIGURABLE NETWORK PROCESSOR By Ian A. Troxel May 2003 Chair: Dr. Alan D. George Department: Electrical and Computer Engineering The fusion of reconfigurable computing (RC) techniques with network processor (NP) designs has opened new doors for packet processing platforms. While previous designs have been static or configurable at best, routing switches, edge switches and network interface cards (NICs) of the future will be able to adapt to network traffic in real-time through dynamic reconfiguration. This paper presents the simulation results of a novel RC-enhanced NP based on the Intel IXP1200 NIC design philosophy. The enhanced NP’s performance is compared to the baseline NP in terms of three normalized traffic patterns and a case-study traffic pattern based on a military application. The results demonstrate that the enhanced NP significantly outperforms the baseline NP in terms of latency, throughput and resource utilization for traffic that is non-uniform.